What is the difference between a Verilog task and a Verilog function?
Electrical Engineering Technical Interview Questions and Answers
1. What is the difference between a Verilog task and a Verilog function?
The following rules distinguish tasks from functions:
A function shall execute in one simulation time unit;
a task can contain time-controlling statements.
A function cannot enable a task;
a task can enable other tasks or functions.
A function shall have at least one input type argument
and shall not have an output or inout type argument;
a task can have zero or more arguments of any type.
A function shall return a single value;
a task shall not return a value.
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